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The core research group studies the interaction of software and modern compute hardware, with an emphasis on improving application performance on multicore systems. The group's work ranges from application architectures, hardware-tuned support libraries, and application performance tuning tools to operating systems support and novel microarchitectures.


Recent Publications
Proving Conflict Serializability for Full Invalidation
Justin E. Gottschlich, Jeremy G. Siek, and Manish Vachharajani
Proceedings of the 2nd Workshop on the Theory of Transactional Memory (WTTM) , September 2010.
Power-Efficient Variation-Aware Photonic On-Chip Network Management
Moustafa Mohamed, Zheng Li, Xi Chen, Li Shang, Alan Mickelson, Manish Vachharajani, and Yihe Sun
The ACM Internatioal Symposium on Low Power Electronics and Design (ISLPED), August 2010.
Nominated For Best Paper Award
An Efficient Software Transactional Memory Using Commit-Time Invalidation [abstract] (PDF)
Justin E. Gottschlich, Manish Vachharajani, and Jeremy G. Siek
Proceedings of the 2010 ACM/IEEE International Symposium on Code Generation and Optimization (CGO'10) , April 2010.
Accept Rate: 39% (29/74).
Best Presentation Award
Large Program Trace Analysis and Compression with ZDDs [abstract] (PDF)
Graham D. Price and Manish Vachharajani
Proceedings of the 2010 ACM/IEEE International Symposium on Code Generation and Optimization (CGO'10) , April 2010.
Accept Rate: 39% (29/74).
Multi-core Acceleration of Chemical Kinetics for Simulation and Prediction [abstract]
John C. Linford, John Michalakes, Manish Vachharajani, and Adrian Sandu
Proceedings of the International Conference on High Performance Computing, Networking, Storage, and Analysis (SC), November 2009.
Accept Rate: 22% (59/261).
All Publications