Publications

Reliability Modeling and Management of Nanophotonic On-Chip Networks [abstract]
Zheng Li, Moustafa Mohammed, Xi Chen, Eric Dudley, Ke Meng, Li Shang, Alan Mickelson, Russ Joseph, Manish Vachharajani, Brian Schwartz, and Yihe Sun
IEEE Transactions on Very Large Scale Integration Systems (TVLSI), 2011.
Proving Conflict Serializability for Full Invalidation
Justin E. Gottschlich, Jeremy G. Siek, and Manish Vachharajani
Proceedings of the 2nd Workshop on the Theory of Transactional Memory (WTTM) , September 2010.
Power-Efficient Variation-Aware Photonic On-Chip Network Management
Moustafa Mohamed, Zheng Li, Xi Chen, Li Shang, Alan Mickelson, Manish Vachharajani, and Yihe Sun
The ACM Internatioal Symposium on Low Power Electronics and Design (ISLPED), August 2010.
Nominated For Best Paper Award
An Efficient Software Transactional Memory Using Commit-Time Invalidation [abstract] (PDF)
Justin E. Gottschlich, Manish Vachharajani, and Jeremy G. Siek
Proceedings of the 2010 ACM/IEEE International Symposium on Code Generation and Optimization (CGO'10) , April 2010.
Best Presentation Award
Large Program Trace Analysis and Compression with ZDDs [abstract] (PDF)
Graham D. Price and Manish Vachharajani
Proceedings of the 2010 ACM/IEEE International Symposium on Code Generation and Optimization (CGO'10) , April 2010.
Multi-core Acceleration of Chemical Kinetics for Simulation and Prediction [abstract]
John C. Linford, John Michalakes, Manish Vachharajani, and Adrian Sandu
Proceedings of the International Conference on High Performance Computing, Networking, Storage, and Analysis (SC), November 2009.
Automating the Generation of Composed Linear Algebra Kernels [abstract] (PDF)
Geoffrey Belter, E. R. Jessup, Ian Karlin, and Jeremy Siek
Proceedings of the International Conference on High Performance Computing, Networking, Storage, and Analysis (SC), November 2009.
A High-performance Low-power Nanophotonic On-chip Network [abstract] (PDF)
Zheng Li, Alan Mickelson, Li Shang, Manish Vachharajani, Dejan Filipovic, Wounjhang Park, and Y. Sun
The ACM Internatioal Symposium on Low Power Electronics and Design (ISLPED), August 2009.
Spectrum: A Hybrid Nanophotonic-electric On-chip Network [abstract]
Zheng Li, Alan Mickelson, Li Shang, Manish Vachharajani, Dejan Filipovic, Wounjhang Park, and Y. Sun
The 46th Annual IEEE Design Automation Conference (DAC), July 2009.
An Efficient Lock-Aware Transactional Memory Implementation [abstract] (PDF)
Justin E. Gottschlich, Jeremy G. Siek, Manish Vachharajani, Dwight Y. Winkler, and Daniel A. Connors
Proceedings of the 2009 ACM International Workshop on the Implementation, Compilation, Optimization of Object-Oriented Languages, Programs and Systems (ICOOOLPS). In conjunction with ECOOP. , July 2009.
Threesomes, With and Without Blame [abstract] (PDF)
Jeremy Siek and Philip Wadler
Proceedings of the 1st International Workshop on Script to Program Evolution (STOP), July 2009.
Exploring the Design Space of Higher-Order Casts [abstract] (PDF)
Jeremy Siek, Ronald Garcia, and Walid Taha
Proceedings of the 18th European Symposium on Programming (ESOP), March 2009.
GPU Acceleration of Numerical Weather Prediction [abstract] (PDF)
John Michalakes and Manish Vachharajani
Parallel Programming Letters (PPL), December 2008.Invited.
Visualizing Potential Parallelism in Sequential Programs [abstract] (PDF)
Graham D. Price, John Giacomoni, and Manish Vachharajani
The 17th International Conference on Parallel Architectures and Compilation Techniques (PACT), October 2008.
Gradual Typing with Unificiation-based Inference [abstract] (PDF)
Jeremy G. Siek and Manish Vachharajani
Proceedings of the 2008 Dynamic Languages Symposium (DLS), July 2008.
C++ Move Semantics for Exception Safety and Optimization in Software Transactional Memory Libraries [abstract] (PDF)
Justin E. Gottschlich, Jeremy G. Siek, and Daniel A. Connors
Proceedings of the 2008 International Workshop on the Implementation, Compilation, Optimization of Object-Oriented Languages, Programs and Systems (ICOOOLPS). In conjunction with ECOOP. , July 2008.
Extending Contention Managers for User-Defined Priority-Based Transactions [abstract] (PDF)
Justin E. Gottschlich and Daniel A. Connors
Proceedings of the 2008 Workshop on Exploiting Parallelism with Transactional Memory and other Hardware Assisted Methods , April 2008.
GPU Acceleration of Numerical Weather Prediction [abstract] (PDF)
John Michalakes and Manish Vachharajani
2008 Workshop on Large-Scale Parallel Processing (LSPP), April 2008.
Gradual Typing with Unification-based Inference [abstract] (PDF)
Jeremy Siek and Manish Vachharajani
University of Colorado Technical Report CU-CS-1039-08, February 2008.
FastForward for Efficient Pipeline Parallelism: A Cache-Optimized Concurrent Lock-Free Queue [abstract] (DOI, PDF)
John Giacomoni, Tipp Moseley, and Manish Vachharajani
Proceedings of the 13th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP), February 2008.
Frame Shared Memory: Line-Rate Networking on Commodity Hardware [abstract] (DOI, PDF)
John Giacomoni, John K. Bennet, Antonio Carzaniga, Douglas C. Sicker, Manish Vachharajani, and Alexander L. Wolf
Proceedings of the 2007 ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS), December 2007.
Discovering the Runtime Structure of Software with Probabilistic Generative Models [abstract] (PDF)
Scott Richardson, Michael Otte, Michael Mozer, Amer Diwan, and Daniel A. Connors
Proceedings of the 2007 International Symposium on Neural Information Processing Systems Workshop for Statistical Learning Techniques for Solving Systems Problems (MLSys), December 2007.
Exploration of Lock-Based Software Transactional Memory [abstract] (PDF)
Justin Gottschlich
M.S. Thesis, Department of Electrical and Computer Engineering, University of Colorado, November 2007.
Simulation and Characterization of Inter-Process Interference on Mulithtreaded and Multicore Architectures [abstract] (PDF)
Joshua Kihm
Ph.D. Thesis, Department of Electrical and Computer Engineering,University of Colorado, November 2007.
DracoSTM: A Practical C++ Approach to Software Transactional Memory [abstract] (PDF)
Justin Gottschlich and Daniel A. Connors
Proceedings of the 2007 The ACM SIGPLAN Symposium on Library-Centric Software Design (LCSD) , October 2007.
Operating System Support for Pipeline Parallelism on Multicore Architectures [abstract] (PDF)
John Giacomoni and Manish Vachharajani
2007 Workshop on Operating Systems Support for Heterogeneous Multicore Architectures (OSHMA), September 2007.
FastForward for Efficient Pipeline Parallelism [abstract] (DOI, PDF, Poster PDF)
John Giacomoni, Tipp Moseley, and Manish Vachharajani
Proceedings of the 16th International Conference on Parallel Architectures and Compilation Techniques (PACT), September 2007. [Poster.]
An Adaptive Fault-Tolerant Memory System for FPGA-based Architectures in the Space Environment [abstract] (PDF)
Dan Fay, Alex Shye, Steve Wichman, and Daniel A. Connors
2007 NASA/ESA Conference on Adaptive Hardware Systems, August 2007.
Investigating the Potential of a GPU-based Math Library [abstract] (PDF)
Dan Fay and Daniel A. Connors
M.S. Thesis, Department of Electrical and Computer Engineering, University of Colorado, August 2007.
Using Process-Level Redundancy to Exploit Multiple Cores for Transient Fault Tolerance [abstract] (PDF)
Alex Shye, Tipp Moseley, Vijay Janapa Reddi, Joseph Blomstedt, and Daniel A. Connors
Proceedings of the 2007 International Conference on Dependable Systems and Networks (DSN), June 2007.
CoGS-Sim: Co-Phase Guided Small-Sample Simulation of Multithreaded and Multicore Architectures [abstract] (PDF)
Joshua Kihm and Daniel A. Connors
Proceedings of The Workshop on Modeling, Benchmarking, and Simulation (MoBS 07) held in conjunction with ISCA-34, June 2007.
Teaching Fault Tolerant FPGA Design for Aerospace Applications [abstract] (PDF)
Dan Fay, Scott Campbell, Greg Miller, and Daniel A. Connors
2007 International Conference on Microelectronic Systems Education, June 2007.
Identifying Potential Parallelism via Loop-centric Profiling [abstract] (PDF)
Tipp Moseley, Dirk Grunwald, Daniel A. Connors, and Ramesh Peri
Proceedings of the 2007 International Conference on Computing Frontiers (CF), May 2007.
Profile Merging and Code Versioning for Automated Profile Guided Optimization Systems [abstract] (PDF)
Rahul Saxena
M.S. Thesis, Department of Electrical and Computer Engineering, University of Colorado, May 2007.
Phase-Guided Small Sample Simulation [abstract] (PDF)
Joshua Kihm, Sam Strom, and Daniel A. Connors
Proceedings of the 2007 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), April 2007.
FastForward for Efficient Pipeline Parallelism [abstract] (PDF)
John Giacomoni, Tipp Moseley, and Manish Vachharajani
University of Colorado Technical Report CU-CS-1028-07, April 2007.
Persistent Code Caching: Exploiting Code Reuse Across Executions and Applications [abstract] (PDF)
Vijay Janapa Reddi, Robert Cohn, Michael Smith, and Daniel A. Connors
Proceedings of the 5th International Conference on Code Generation and Optimization (CGO), March 2007.
Best Presentation Award
Toward a Toolchain for Pipeline Parallel Programming on CMPs [abstract] (PDF)
John Giacomoni, Tipp Moseley, Graham Price, Brian Bushnell, Manish Vachahrajani, and Dirk Grunwald
Proceedings of the 2007 Workshop on Software Tools for Multicore Systems (STMCS), March 2007.
Harnessing Chip-Multiprocessors with Concurrent Threaded Pipelines [abstract] (PDF)
John Giacomoni and Manish Vachharajani
University of Colorado Technical Report CU-CS-1024-07, January 2007.
FastForward for Concurrent Threaded Pipelines [abstract] (PDF)
John Giacomoni, Tipp Moseley, and Manish Vachharajani
University of Colorado Technical Report CU-CS-1023-07, January 2007.
Model Based Load Indices (MBLI) for Scientific Simulation [abstract] (PDF)
Stefan Muszala
Ph.D. Thesis, Department of Electrical and Computer Engineering,University of Colorado, January 2007.
A Case for Compressing Traces with BDDs [abstract] (PDF, Google Tech Talk)
Graham D. Price and Manish Vachharajani
IEEE Computer Architecture Letters (CAL), Volume 5, Number 2, December 2006.
A Detailed Study of the Numerical Accuracy of GPU-Implemented Math Functions [abstract] (PDF)
Dan Fay, Ali Sazegari, and Daniel A. Connors
Supercomputing '06 Workshop on General-Purpose GPU Computing: Practice And Experience, November 2006.
Understanding Cache Interference [abstract] (PDF)
Alex Settle
Ph.D. Thesis, Department of Electrical and Computer Engineering,University of Colorado, November 2006.
FShm: High-rate Frame Manipulation in Kernel and User-Space [abstract] (PDF)
John Giacomoni, John K. Bennet, Antonio Carzaniga, Manish Vachharajani, and Alexander L. Wolf
University of Colorado Technical Report CU-CS-1015-06, October 2006.
Using LoopProf to Identify Parallelism in Sequential Programs [abstract] (PDF)
Tipp Moseley, Vasanth Tovinkere, Ram Ramanujan, Daniel A. Connors, and Dirk Grunwald
Proceedings of the Workshop on Binary Instrumentation and Applications (WBIA), October 2006.
Transient Fault Tolerance via Dynamic Process Redundancy [abstract] (PDF)
Alex Shye, Vijay Janapa Reddi, Tipp Moseley, and Daniel A. Connors
Proceedings of the Workshop on Binary Instrumentation and Applications (WBIA), October 2006.
Partial Reconfiguration Across FPGAs [abstract] (PDF)
Steve Wichman, Sammit Adyha, Scott Ahrens, Rohan Ambli, Brad Alcorn, Dan Fay, and Daniel A. Connors
Proceedings of the International Conference on Military and Aerospace Programmable Logic Devices (MAPLD), September 2006.
Hardware-Compiler Co-Design for Adjustable Data Power Savings [abstract] (PDF)
Hillery Hunter, Wen-mei Hwu, and Daniel A. Connors
International Journal of Embedded Systems, June 2006.
Deconstructing Hardware Usage for General Purpose Computation on GPUs (GPGPU) [abstract] (PDF)
Budyanto Himawan and Manish Vachharajani
Proceedings of the 2006 Workshop on Duplicating, Debunking, and Deconstructing (WDDD), June 2006.
Improved Stride Prefetching using Extrinsic Stream Characteristics [abstract] (PDF)
Hassan Al-Aukhni, James Holt, and Daniel A. Connors
IEEE International Symposium on Performance Analysis of Systems and Software, March 2006.
An Evolving Curriculum to Match the Evolution of Reconfigurable Computing Platforms [abstract] (PDF)
Graham Schelle, Dan Fay, Dirk Grunwald, Daniel A. Connors, and John Bennet
The 1st International Workshop on Reconfigurable Computing Education (RC education 2006), March 2006.
Exploiting Parallelism and Structure to Accelerate the Simulation of Chip Multi-processors [abstract] (PDF)
David Penry, Dan Fay, Graham Schelle, David August , and Daniel A. Connors
12th International Symposium on High-Performance Computer Architecture, February 2006.
The Design of Cost-Effective Stride-Prefetching for Modern Processors [abstract] (PDF)
Hassan Al-Sukhni, James Holt, and Daniel A. Connors
4th Workshop on Memory Performance Issues (WMPI-2006), February 2006.
Dynamic Compiler Driven Control for Microprocessor Energy and Performance [abstract] (PDF)
Qiang Wu, Vijay Janapa Reddi, Youfeng Wu, Daniel A. Connors, David Brooks, Margaret Martonosi, and Douglas Clark
IEEE Micro, Volume 26, Number 1, January 2006.
IEEE Micro Top Pick in Computer Architecture
A Dynamically Reconfigurable Cache for Multithreaded Processors [abstract] (PDF)
Alex Settle, Daniel A. Connors, Enric Gibert, and Antonio Gonzalez
Journal of Embedded Computing: Special Issue on Single-Chip Multi-core Architectures, December 2005.
Chip Multi-Processor Scalability for Single-Threaded Applications [abstract] (PDF)
Neil Vachharajani, Matthew Iyer, Chinmay Ashok, Manish Vachharajani, David I. August, and Daniel A. Connors
Proceedings of the 2005 Workshop on Design, Architecture and Simulation of Chip Multi-Processors (dasCMP), November 2005.
A Dynamic Compilation Framework for Controlling Microprocessor Energy and Performance [abstract] (PDF)
Qiang Wu, Vijay Janapa Reddi, Youfeng Wu, Daniel A. Connors, David Brooks, Margaret Martonosi, and Douglas Clark
Proceedings of the 38th IEEE/ACM International Symposium on Microarchitecture (MICRO), November 2005.
Best Paper Award
Deploying Dynamic Code Transformation in Modern Computing Environments [abstract] (PDF)
Vijay Janapa Reddi
M.S. Thesis, Department of Electrical and Computer Engineering, University of Colorado, November 2005.
Hardware-Compiler Co-Design for Adjustable Data Power Savings [abstract] (PDF)
Hillery Hunter, Erik Nystrom, Wen-mei Hwu, and Daniel A. Connors
Proceedings of the 7th Workshop on Media and Streaming Processors, November 2005.
Identifying and Exploiting Memory Access Characteristics for Prefetching Linked Data Structures [abstract] (PDF)
Hassan Al-Sukhni
Ph.D. Thesis, Department of Electrical and Computer Engineering,University of Colorado, November 2005.
Methods for Modeling Resource Contention on Simultaneous Multithreading Processors [abstract] (PDF)
Tipp Moseley, Joshua Kihm, Daniel A. Connors, and Dirk Grunwald
Proceedings of the 2005 International Conference on Computer Design (ICCD), October 2005.
Code Coverage Testing Using Hardware Performance Monitoring Support [abstract] (PDF)
Alex Shye, Matthew Iyer, Vijay Janapa Reddi, and Daniel A. Connors
Proceedings of the 6th International Symposium on Automated andAnalysis-Driven Debugging (AADEBUG), September 2005.
Statistical Simulation of Multithreaded Architectures [abstract] (PDF)
Joshua Kihm and Daniel A. Connors
Proceedings of 13th Annual Meeting of the IEEE International Symposiumon Modeling, Analysis, and Simulation of Computer Systems, September 2005.
Persistence in Dynamic Code Transformation Systems [abstract] (PDF)
Vijay Janapa Reddi, Daniel A. Connors, and Robert Cohn
Proceedings of the Workshop on Binary Instrumentation and Applications (WBIA), September 2005.
The Promise of Load-Balancing the Parameterization of Moist Convection onMulti-Processor Systems [abstract] (PDF)
Stefan Muszala, James Hack, Daniel A. Connors, and Gita Alaghband
Journal of Atmospheric and Oceanic Technology, July 2005.
Understanding the Impact of Inter-Thread Cache Interference on ILP in Modern SMT Processors [abstract] (PDF)
Joshua Kihm, Alex Settle, Andy Janiszewski, and Daniel A. Connors
The Journal of Instruction Level Parallelism (JILP), Volume 7, June 2005.
Rapid Development of Flexible Validated Processor Models [abstract] (PDF, PostScript)
David A. Penry, Manish Vachharajani, and David I. August
Proceedings of the Workshop on Modeling, Benchmarking, and Simulation (MoBS), June 2005.
Dynamic Run-time Architecture Techniques for Enabling Continuous Optimization [abstract] (PDF)
Tipp Moseley, Alex Shye, Vijay Janapa Reddi, Matthew Iyer, Dan Fay, Joshua Kihm, Alex Settle, Dirk Grunwald, and Daniel A. Connors
Proceedings of the 2005 International Conference on Computing Frontiers (CF)., May 2005.
A Mathematical Model for Accurately Balancing Co-Phase Effects in Simulated Multithreaded Systems [abstract] (PDF)
Joshua Kihm, Tipp Moseley, and Daniel A. Connors
Proceedings of The Workshop on Modeling, Benchmarking, and Simulation (MoBS 05) held in conjunction with ISCA-32, May 2005.
Exploring the Potential of Performance Monitoring Hardware to Support Run-time Optimization [abstract] (PDF)
Alex Shye
M.S. Thesis, Department of Electrical and Computer Engineering, University of Colorado, May 2005.
Analysis of Hardware Acceleration in Reconfigurable Embedded Systems [abstract] (PDF)
Mathew Ouellette and Daniel A. Connors
Proceedings of the 12th Reconfigurable Architectures Workshop (RAW 2005), April 2005.
Finding Parallelism for Future EPIC Machines [abstract] (PDF)
Matthew Iyer, Chinmay Ashok, Joshua Stone, Neil Vachharajani, Daniel A. Connors, and Manish Vachharajani
Proceedings of the Fourth Workshop on Explicitly Parallel Instruction Computer Architectures and Compiler Technology (EPIC), March 2005.
Analysis of Path Profiling Information Generated with Performance Monitoring Hardware [abstract] (PDF)
Alex Shye, Matthew Iyer, Tipp Moseley, Dan Fay, Vijay Janapa Reddi, and Daniel A. Connors
Proceedings of the 9th Workshop on Interaction between Compilers and Computer Architecture (INTERACT), February 2005.
Compiler Optimization-Space Exploration [abstract] (Research Notes, PDF)
Spyridon Triantafyllis, Manish Vachharajani, and David I. August
The Journal of Instruction-level Parallelism (JILP), February 2005.
RIFLE: An Architectural Framework for User-Centric Information-Flow Security [abstract] (PDF, PostScript)
Neil Vachharajani, Matthew J. Bridges, Jonathan Chang, Ram Rangan, Guilherme Ottoni, Jason A. Blome, George A. Reis, Manish Vachharajani, and David I. August
Proceedings of the 37th International Symposium on Microarchitecture (MICRO), December 2004.
Implementation of Fine-Grained Cache Monitoring for Improved SMT Scheduling [abstract] (PDF)
Joshua Kihm and Daniel A. Connors
Proceedings of the 2004 International Conference on Computer Design, October 2004.
Architectural Support for Enhanced SMT Job Scheduling [abstract] (PDF)
Alex Settle, Joshua Kihm, and Daniel A. Connors
Proceedings of the 13th International Symposium on Parallel Architectures and Compilation Techniques, October 2004.
Facilitating Reuse in Hardware Models with Enhanced Type Inference [abstract] (PDF, PostScript)
Manish Vachharajani, Neil Vachharajani, Sharad Malik, and David I. August
The IEEE/ACM/IFIP Second International Conference on Hardware/Software Codesign and System Synthesis (ISSS), September 2004.
A Very Fast Simulated Annealing Scheduler for Radioactive Transfer Data in Climate Models [abstract] (PDF)
Stefan Muszala, Gita Alaghband, Daniel A. Connors, and James Hack
Proceedings of the 17th International Conference on Parallel and Distributed Computing Systems (PDCS), September 2004.
Predictable Fine Grained Cache Behavior for Enhanced Simulaneous Multithreading (SMT) Scheduling [abstract] (PDF)
Joshua Kihm, Andy Janiszewski, and Daniel A. Connors
Proceedings of the 2004 Conference on Computing, Communications, and Technologies., August 2004.
PIN: A Binary Instrumentation Tool in Computer Architecture Research and Education [abstract] (PDF)
Vijay Janapa Reddi, Alex Settle, Daniel A. Connors, and Robert Cohn
Proceedings of the 7th International Workshop on Computer Architecture Education (WCAE), June 2004.
Compiler Controlled Register Stack Management for the Intel Itanium Architecture [abstract] (PDF)
Alex Settle, Dan Lavery, Gerolf Hoflehner, and Daniel A. Connors
Proceedings of the 3rd Workshop on Explicitly Parallel Instruction Computing Architectures and Compiler Techniques, March 2004.
Using Existing Performance Monitoring Hardware to Enable Power Prediction in Microprocessors [abstract] (PDF)
Garret Holthaus
M.S. Thesis, Department of Electrical and Computer Engineering, University of Colorado, December 2003.
Compiler-Directed Content-Based Prefetching for Dynamic Data Structures. [abstract] (PDF)
Hassan Al-Sukhni, Ian Bratt, and Daniel A. Connors
Proceedings of the 12th International Symposium on Parallel Architectures and Compiler Techniques, October 2003.
Analysis and Design of Architecture Systems for Speech Recognition on Modern Handheld-Computing Devices. [abstract] (PDF)
Andreas Hagen, Bryan Pellom, and Daniel A. Connors
Proceedings of the of the 11th International Symposium on Hardware/Software Codesign., October 2003.
Vertical Optimization of Particle in Cell Code Simulation [abstract] (PDF)
Viktor Przebinda
M.S. Thesis, Department of Electrical and Computer Engineering, University of Colorado, May 2003.
Optimization for the Intel Itanium Architecture Register Stack. [abstract] (PDF)
Alex Settle, Daniel Lavery, Gerolf Hoflehner, and Daniel A. Connors
Proceedings of the 1st Conference on Code Generation and Optimization, March 2003.
Compiler-Directed Resource Management for Active Code Regions [abstract] (PDF)
Ravikrishnan Sree, Alex Settle, and Daniel A. Connors
Proceedings of the 7th Workshop on Interaction between Compilers and Computer Architecture, February 2003.
Predicate-Based Transformations to Eliminate Control and Data-Irrelevant Cache Misses. [abstract] (PDF)
Alex Settle, Ian Bratt, and Daniel A. Connors
Proceedings of the 1st Workshop on Explicitly Parallel Instruction Computing Architectures and Compilers, December 2001.
Hardware Support for Dynamic Activation of Compiler-Directed Computation Reuse. [abstract] (PDF)
Daniel A. Connors and Wen-mei Hwu
Proceedings of the 9th International Conference on Architecture Support for Programming Languages and Operating Systems, November 2000.
Compiler-Directed Early Load-Address Generation. [abstract] (PDF)
Ben-Chung Cheng, Daniel A. Connors, and Wen-mei Hwu
Proceedings of the 31th International Symposium on Microarchitecture, December 1999.
Run-Time Cache Bypassing. [abstract] (PDF)
Theresa Johnson, Daniel A. Connors, and Wen-mei Hwu
IEEE Transactions on Computers., December 1999.
Compiler-Directed Dynamic Computation Reuse: Rationale and Initial Results. [abstract] (PDF)
Daniel A. Connors and Wen-mei Hwu
Proceedings of the 32nd International Symposium on Microarchitecture, November 1999.
An Architecture Framework for Introducing Predicated Execution into Embedded Microprocessors. [abstract] (PDF)
Daniel A. Connors, David August, Jean-Michel Puiatti, and Wen-mei Hwu
Proceedings of the 5th International Euro-Par Conference, August 1999.